Programmable Logic Device with an 8-stage cascade of 64K-bit Asynchronous SRAMs

The first implementation of a new programmable logic device using LUT(Look-Up Table) cascade architecture is developed in 0.35um CMOS logic process. Eight 64Kb asynchronous SRAMs are simply connected to form an LUT cascade with a few additional circuits. Benchmark results show that it has a competitive performance to FPGAs. 1. Introduction RAMs and PLAs (Programmable Logic Array) are used for programmable logic devices that realize multiple-output combinational logic functions. However, when the number of inputs and/or outputs for the target function is large, these devices require excessive amounts of hardware. Thus, FPGAs (Field Programmable Gate Arrays) are often used. However, the area and delay for interconnections among logic cells are much larger than those for logic elements. Therefore the prediction of the performance of the FPGA is difficult without complete physical design. To solve these problems, an LUT cascade architecture that is composed of a serial connection of large-scale memories has been developed [1]. The LUT cascade uses relatively larger LUTs (1kb-1Mb), and the interconnections between LUTs are limited to the adjacent cells in the cascade. This is quite different from the two-dimensional structure of FPGAs with smaller (16b-64b) LUTs. The large area for the interconnections in an FPGA is absorbed in the larger LUTs in the cascade. So, the cascade is re-configured by only changing the contents of the LUTs. 2. Design of LUT Cascade LSI An LUT block is mainly composed of an asynchronous 64kbit SRAM with 13bit address inputs and 8bit data I/Os. Since the memory should be operated as a data-path in LUT cascade architecture, an asynchronous SRAM is employed. In our design, each LUT block has 17 inputs: 8 bits are connected to the outputs of the preceding LUT, and 9 bits are from the external inputs (X). Then 13 of the 17 inputs are selected by crossover switches to form the actual address inputs of an LUT, and the unselected 4 signals can be used as intermediate outputs through Y terminals. This configuration enables to extend the number of allowable input/output signals from 48/8 (without crossover switches) to 76/36 (with crossover switches) for an 8-LUT cascade. This achieves an increase in the number of functions realizable with the LUT cascade. The LUT cascade LSI is simply realized by a cascade connection of LUT blocks. Each LUT block also has connections to the common address lines used for programming and testing. When a TEST (Program) …